Data rate for spi seems to be an ongoing source of question for people, so with the next release I’m going to make some slight changes to it. The value, nominally, sets up the speed that the spi clock runs at. It does this by specifying a divider for the system clock rate. However, right now there isn’t a direct mapping. 0 maps to a /2 divider, 1 to /3, and 2 maps to /4. (A quirk of how I set up some of the timing code initially).
The first of the two changes I will be making in the near future are making sure that the value maps directly to the divider - e.g a speed of 2 means an 8Mhz clock on a 16Mhz system, or a 24Mhz clock on a 48Mhz system. The second one will be providing a series of definitions so that you can specify the speed you want the spi clock to run at in Mhz/Khz, and do the math/juggling behind the scenes to get as close as possible.
Of course, with hardware spi you don’t get any rate you want, there are limits becuase the dividers are powers of two. For example, on the avr running at 16Mhz, you can have 8Mhz, 4Mhz, 2Mhz, 1mhz, 500khz, 250khz, and 125khz.
On the teensy 3, there’s a bit more flexibility because while the dividers are powers of 2, you can optionally multiply the divider by 2, 3, 5, or 7 to give you a bit more flexibility in the clock rates you run at.